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vhdl

concurrent and sequential statements in VHDL

发布于 2020-12-04 14:44:23

I have a fundamental question on VHDL.

Consider the following process:

process(Clk)
begin
if(rising_edge(Clk)) then
  a <= data_in;
  b <= a;
  c <= b;
  data_out <= c;
end if;
end process;

The above process acts as a delay register, where data_in is output to data_out after 4 clock cycles.

From my understanding this happens because signals are assigned parallelly. But then why does the statements inside a process called sequential?

For example:

process(Clk)
begin
if(rising_edge(Clk)) then
  a <= b or c;
  a <= b and c;
end if;
end process;

In the above process the 'a' takes the value from the 2nd statement and I understand, how it works in a sequential way unlike the first process.

Please help.

Questioner
vipin
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Matthew Taylor 2020-12-05 00:01:10

It's actually very simple: all statements inside a VHDL process are executed sequentially, in order, from top to bottom, no exceptions. However,

  1. the left hand side of a signal assignment operator (<=) does not take its new value until the process (and all other processes) have suspended (either hit the bottom or hit a wait statement) and

  2. if you assign to a signal again (as in your second example) the last assignment executed overwrites the previous ones.

Now you know that, simulate the above two processes in your head and you will see that they behave as you say they will. (The statements in your first example are NOT executed in parallel. But because of (1) above, it seems like they are.)

vipin 2020-12-04 15:02:25

yes. simple. thanks a lot.

vipin 2020-12-04 15:23:48

May I ask, How does the variables get updated then? Is it also sequential but doesnt abide by the rule (1).

Matthew Taylor 2020-12-04 16:00:44

@vipin No. Variables get updated immediately.

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