verilog - Quartus Prime在$ error命令上抛出错误

我的以下代码有问题，如果我的输入数不能被我的输出数整除，那么下面的代码应该在编译时简单地引发错误。

module multiplexer #(parameter N_INPUTS, parameter N_OUTPUTS) (in, out, select);

    generate
        if (N_INPUTS % N_OUTPUTS != 0) begin
            $error("%m ** Illegal Parameter ** NUMBER OF INPUTS(%d) does not divide into NUMBER OF OUTPUTS(%d)", N_INPUTS, N_OUTPUTS);
        end
    endgenerate

    input wire [N_INPUTS-1:0] in;
    input wire [$clog2(N_INPUTS/N_OUTPUTS) - 1:0] select;
    output wire [N_OUTPUTS-1:0] out;

    always @ (select, in) begin
        out = in[(select + 1) * N_OUTPUTS - 1:(select + 1) * N_OUTPUTS - N_OUTPUTS];
    end

endmodule

但是当我进行分析时，Quartus总是向我抛出此错误：

Error (10170): Verilog HDL syntax error at multiplexer.v(5) near text: "$error";  expecting "end". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.

我开始怀疑Quartus的编译器是否支持$ error命令（这是我第一次使用它）。

非常感谢您提供有关此主题的帮助，因为我仍然是该领域的初学者:)