How to write new line to file in VHDL?

I would like to separate my data with new line character in an output file, but the following codes result in error "can't resolve overload for procedure call":

write(out_line, "\n"); 
write(out_line, ""); 
write(out_line, '');

An example code how I want to use it:

ENTITY writer IS 
PORT ( clk : IN STD_LOGIC := '0'; start : IN STD_LOGIC := '0');
END ENTITY;

ARCHITECTURE arch OF writer IS
    SIGNAL vect : STD_LOGIC_VECTOR (2 downto 0) := "000";
    TYPE state_type IS (init, write_file);
    SIGNAL state : state_type := init;
BEGIN
    PROCESS (clk, start)
        FILE out_file : text;
        VARIABLE out_line : line;
    BEGIN
       IF rising_edge(clk) THEN
           CASE state IS 
               WHEN init => 
                   IF start = '1' THEN
                       state <= write_file;
                   ELSE 
                       state <= init;
                   END IF;
               WHEN write_file =>
                   state => init;

                   FOR i IN 0 TO 10 LOOP
                       write(out_line, vect);
                       writeline(out_file, out_line);
                       -- write(out_line, "\n"); <-- 
                       -- write(out_line, ""); <-- 
                       -- write(out_line, ''); <-- None of these work
                       writeline(out_file, out_line); 
                   END LOOP;
           END CASE;
       END IF;
   END PROCESS;
END ARCHITECTURE;
               

So I would like to know, is it possible in VHDL? If yes, how?