This is specific to VHDL. When you define port with a mode you are giving that port certain architectural properties. Data flows in to an entity from a port with mode IN. Data only flow out of an entity for port with mode OUT. Thus you can not read an OUT port inside of your entity. Assume you have a foo: out std_logic; You CANNOT write an expression that says fi <= foo; This should cause an error when you compile.
I am not making a case to make foo: inout std_logic; but that would be one rational for maybe doing it. The inout allows for assignment and reading.
If I didn't need to have the port as an input on the entity, I would have assigned it as a an OUT personally. I would have used an internal signal for assignment and reading, and driven the out port from the signal.
FYI: VHDL 2008 allows reading of output ports
A mode out port in -2008 matches the behavior of mode buffer which can be used with implementations relying on earlier revisions of the standard.